A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI

Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 x 1800 µm²

Safety and Revisit Related to Discharge the Sixty-one Spanish Emergency Department Medical Centers Without Hospitalization in Patients with COVID-19 Pneumonia. A Prospective Cohort Study UMC-Pneumonia COVID-19

Background: Information is needed on the safety and efficacy of direct discharge from the emergency department (ED) of patients with COVID-19 pneumonia. Objectives: The objectives of the study were to study the variables associated with discharge from the ED in patients presenting with COVID-19 pneumonia, and study ED revisits related to COVID-19 at 30 days (EDR30d). Methods: Multicenter study of the SIESTA cohort including 1198 randomly selected COVID patients in 61 EDs of Spanish medical centers from March 1, 2020, to April 30, 2020. We collected baseline and related characteristics of the acute episode and calculated the adjusted odds ratios (aOR) for ED discharge. In addition, we analyzed the variables related to EDR30d in discharged patients. Results: We analyzed 859 patients presenting with COVID-19 pneumonia, 84 (9.8%) of whom were discharged from the ED. The variables independently associated with discharge were being a woman (aOR 1.890; 95%CI 1.176-3.037), age 1200/mm(3) (aOR 4.667; 95%CI 1.045-20.839). The EDR30d of the ED discharged group was 40.0%, being lower in women (aOR 0.368; 95%CI 0.142-0.953). A total of 130 hospitalized patients died (16.8%) as did two in the group discharged from the ED (2.4%) (OR 0.121; 95%CI 0.029-0.498). Conclusion: Discharge from the ED in patients with COVID-19 pneumonia was infrequent and was associated with few variables of the episode. The EDR30d was high, albeit with a low mortality

The evolution of the ventilatory ratio is a prognostic factor in mechanically ventilated COVID-19 ARDS patients

Background: Mortality due to COVID-19 is high, especially in patients requiring mechanical ventilation. The purpose of the study is to investigate associations between mortality and variables measured during the first three days of mechanical ventilation in patients with COVID-19 intubated at ICU admission. Methods: Multicenter, observational, cohort study includes consecutive patients with COVID-19 admitted to 44 Spanish ICUs between February 25 and July 31, 2020, who required intubation at ICU admission and mechanical ventilation for more than three days. We collected demographic and clinical data prior to admission; information about clinical evolution at days 1 and 3 of mechanical ventilation; and outcomes. Results: Of the 2,095 patients with COVID-19 admitted to the ICU, 1,118 (53.3%) were intubated at day 1 and remained under mechanical ventilation at day three. From days 1 to 3, PaO2/FiO2 increased from 115.6 [80.0-171.2] to 180.0 [135.4-227.9] mmHg and the ventilatory ratio from 1.73 [1.33-2.25] to 1.96 [1.61-2.40]. In-hospital mortality was 38.7%. A higher increase between ICU admission and day 3 in the ventilatory ratio (OR 1.04 [CI 1.01-1.07], p = 0.030) and creatinine levels (OR 1.05 [CI 1.01-1.09], p = 0.005) and a lower increase in platelet counts (OR 0.96 [CI 0.93-1.00], p = 0.037) were independently associated with a higher risk of death. No association between mortality and the PaO2/FiO2 variation was observed (OR 0.99 [CI 0.95 to 1.02], p = 0.47). Conclusions: Higher ventilatory ratio and its increase at day 3 is associated with mortality in patients with COVID-19 receiving mechanical ventilation at ICU admission. No association was found in the PaO2/FiO2 variation

A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs

Desde la invención en 1960 del transistor de efecto de campo metal-óxido-semiconductor (MOSFET por sus siglas en inglés), la industria de semiconductores no ha cesado en la creación de nuevas invenciones para reducir las dimensiones de los transistores de la escala micrométrica (< 10-μm) a las dimensiones actuales de 7-14-nm, o incluso para la creación del nuevo nódulo tecnológico de 5-nm, cuya fabricación está prevista para 2020-2021, con el objetivo de fabricar dispositivos más fiables y circuitos más avanzados, con miles de millones de transistores por chip. Con todos los beneficios que aporta el escalado aplicado a las dimensiones de los transistores en cuanto a potencia, área y rendimiento, el hecho de aproximarse a la escala atómica acarrea el aumento de variaciones en el rendimiento intrínseco de los transistores, por lo que la fiabilidad de los dispositivos y circuitos fabricados puede verse seriamente comprometida. De esta forma, las variaciones en los parámetros de transistores fabricados, como la tensión umbral o la movilidad, así como su degradación a lo largo del tiempo, han pasado a ser un motivo de preocupación en el diseño de circuitos integrados con dispositivos nanométricos. Además, el aumento significativo en las corrientes de fuga en los transistores debidas al escalado del aislante de puerta, ha favorecido la utilización de nuevos y más complejos dieléctricos de puerta para incrementar la fiabilidad de los dispositivos, como el oxinitruro de silicio (SiON) o los aislantes de puerta de metal (HKMG). Asimismo, también han surgido dispositivos con nuevas geometrías tales como los FinFETs, FDSOI o MuGFETs para continuar con el escalado y poder tener mejor control de los efectos de canal corto. La variabilidad en los parámetros de los transistores, estocástica por naturaleza, debe ser caracterizada de forma masiva para poder capturar aquellas variaciones con un muestreo estadístico representativo. Las fuentes de variabilidad están divididas en dos grupos: primero, la variabilidad a tiempo cero, que tiene lugar durante el proceso de fabricación y que consiste en un cambio permanente (ya sea aleatorio o sistemático) en los parámetros del dispositivo; y segundo, la variabilidad dependiente del tiempo, que tiene lugar a lo largo del tiempo cuando los dispositivos o circuitos funcionan en condiciones nominales. Esta incluye efectos transitorios como el Random Telegraph Noise, mecanismos de degradación o envejecimiento, como el Hot Carrier Injection, Bias Temperature Instability, Time Dependent Dielectric Breakdown, Stress Induced Leakage Currents, etc., pueden derivar en una degradación progresiva o en un fallo permanente. Con el objetivo de reducir o mitigar los efectos de la variabilidad, se requieren nuevas técnicas de diseño de circuitos que tengan en cuenta el impacto combinado de la variabilidad de proceso, junto con la variabilidad dependiente del tiempo en nodos tecnológicos avanzados. Dichas técnicas emplean precisos modelos compactos basados en la caracterización estadística de dispositivos individuales. En este sentido, proporcionar una caracterización estadísticamente precisa de los efectos de la variabilidad en tecnologías CMOS modernas, ha resultado ser clave para lograr circuitos integrados verdaderamente fiables. En este sentido, esta tesis pretende contribuir a la caracterización masiva y a la estimación precisa del tiempo de vida de tecnologías nanométricas CMOS mediante el análisis exhaustivo de datos estadísticos. Para poder llevarlo a cabo, todos los inconvenientes relacionados con las técnicas convencionales de caracterización en serie basadas en obleas de silicio más comunes, que exigen meses o incluso años de caracterización ininterrumpida de dispositivos, se han solventado gracias al nuevo diseño de un circuito integrado versátil basado en una estructura matricial de transistores MOSFET, junto con el diseño de un sistema de caracterización totalmente automatizado dedicado a la caracterización estadística de transistores MOSFET en circuitos integrados.Since the invention in 1960 of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the CMOS semiconductor industry has invariably invented new feats to progressively reduce the minimum gate length, from the micrometer scale (< 10-μm) to the nowadays 7-14-nm gate lengths or the new 5-nm technology node predicted to be manufactured in 2020-2021, all with the aim of fabricating more reliable devices and even more advanced circuits and systems, with billions of transistors per chip. With all the benefits that transistor size scaling brings to power, area and performance, approaching the atomic scale poses an important peril: the increase of variations of the transistor’s intrinsic performance, thus critically compromising the fundamental reliability of the fabricated devices and circuits. In this way, variations of fabricated transistor parameters, like for instance threshold voltage or mobility, as well as their degradation during circuit functionality, have become an increasing concern in nanometer integrated circuit design. Moreover, a significant increase of gate leakage current has emerged due to the scaling in the thickness of the transistor’s insulator. In this scenario, to increase performance and reliability of the fabricated devices, new and more complex stack materials have been introduced, such as Silicon oxynitride (SiON), High-K Metal gate insulators (HKMG) and new devices geometries like FinFETs, FDSOI or MuGFETs have emerged in ultra-scaled technology nodes to continue with the scaling trend and have better control of the short channel effects. The variability in the transistor parameters, stochastic by nature, must be massively characterized to capture those variations with a representative and sound statistical sampling. Variability sources are divided in two different types: first, the time-zero variability, typically known as process variability which occurs during the fabrication process and consists in a permanent either random or systematic, shift of the device parameters; second, the time-dependent variability, which occurs during device or circuit operation over time and includes transient effects like Random Telegraph Noise, and degradation mechanisms or aging effects, like Hot Carrier Injection, Bias Temperature Instability, Time Dependent Dielectric Breakdown, Stress Induced Leakage Current, etc., which are potential sources of device and IC variability that can lead transistors to a progressive degradation or to a permanent failure. To reduce or mitigate variability effects, novel variability-aware circuit design techniques are required to assess the combined impact of time-zero and time-dependent variability in advanced technology nodes. Variability-aware techniques utilize accurate compact models, which are based in statistical characterization of individual MOSFET devices. In this regard, providing statistically accurate characterization of TZV and TDV effects in modern CMOS technologies has, therefore, become a key step in the path towards attaining truly reliable integrated circuits. In this context, this thesis will contribute to the characterization and lifetime prediction of nanometer CMOS technologies through a thorough study of an extensive statistical data samples. To do so, issues related to typical serial characterization techniques, which require months or even years of continuous non-stop device testing, are overcome thanks to a novel and versatile array-based IC chip design in conjunction with a full-custom characterization framework. These two key elements, the IC and the framework, can effectively be utilized to statistically characterize the impact of different device variability sources in nanometer-scale MOSFETs while significantly and outstandingly reducing the required characterization time

A versatile framework for the statistical characterization of CMOS time-zero and time-dependent variability with array-based ICs

Desde la invención en 1960 del transistor de efecto de campo metal-óxido-semiconductor (MOSFET por sus siglas en inglés), la industria de semiconductores no ha cesado en la creación de nuevas invenciones para reducir las dimensiones de los transistores de la escala micrométrica (< 10-μm) a las dimensiones actuales de 7-14-nm, o incluso para la creación del nuevo nódulo tecnológico de 5-nm, cuya fabricación está prevista para 2020-2021, con el objetivo de fabricar dispositivos más fiables y circuitos más avanzados, con miles de millones de transistores por chip. Con todos los beneficios que aporta el escalado aplicado a las dimensiones de los transistores en cuanto a potencia, área y rendimiento, el hecho de aproximarse a la escala atómica acarrea el aumento de variaciones en el rendimiento intrínseco de los transistores, por lo que la fiabilidad de los dispositivos y circuitos fabricados puede verse seriamente comprometida. De esta forma, las variaciones en los parámetros de transistores fabricados, como la tensión umbral o la movilidad, así como su degradación a lo largo del tiempo, han pasado a ser un motivo de preocupación en el diseño de circuitos integrados con dispositivos nanométricos. Además, el aumento significativo en las corrientes de fuga en los transistores debidas al escalado del aislante de puerta, ha favorecido la utilización de nuevos y más complejos dieléctricos de puerta para incrementar la fiabilidad de los dispositivos, como el oxinitruro de silicio (SiON) o los aislantes de puerta de metal (HKMG). Asimismo, también han surgido dispositivos con nuevas geometrías tales como los FinFETs, FDSOI o MuGFETs para continuar con el escalado y poder tener mejor control de los efectos de canal corto. La variabilidad en los parámetros de los transistores, estocástica por naturaleza, debe ser caracterizada de forma masiva para poder capturar aquellas variaciones con un muestreo estadístico representativo. Las fuentes de variabilidad están divididas en dos grupos: primero, la variabilidad a tiempo cero, que tiene lugar durante el proceso de fabricación y que consiste en un cambio permanente (ya sea aleatorio o sistemático) en los parámetros del dispositivo; y segundo, la variabilidad dependiente del tiempo, que tiene lugar a lo largo del tiempo cuando los dispositivos o circuitos funcionan en condiciones nominales. Esta incluye efectos transitorios como el Random Telegraph Noise, mecanismos de degradación o envejecimiento, como el Hot Carrier Injection, Bias Temperature Instability, Time Dependent Dielectric Breakdown, Stress Induced Leakage Currents, etc., pueden derivar en una degradación progresiva o en un fallo permanente. Con el objetivo de reducir o mitigar los efectos de la variabilidad, se requieren nuevas técnicas de diseño de circuitos que tengan en cuenta el impacto combinado de la variabilidad de proceso, junto con la variabilidad dependiente del tiempo en nodos tecnológicos avanzados. Dichas técnicas emplean precisos modelos compactos basados en la caracterización estadística de dispositivos individuales. En este sentido, proporcionar una caracterización estadísticamente precisa de los efectos de la variabilidad en tecnologías CMOS modernas, ha resultado ser clave para lograr circuitos integrados verdaderamente fiables. En este sentido, esta tesis pretende contribuir a la caracterización masiva y a la estimación precisa del tiempo de vida de tecnologías nanométricas CMOS mediante el análisis exhaustivo de datos estadísticos. Para poder llevarlo a cabo, todos los inconvenientes relacionados con las técnicas convencionales de caracterización en serie basadas en obleas de silicio más comunes, que exigen meses o incluso años de caracterización ininterrumpida de dispositivos, se han solventado gracias al nuevo diseño de un circuito integrado versátil basado en una estructura matricial de transistores MOSFET, junto con el diseño de un sistema de caracterización totalmente automatizado dedicado a la caracterización estadística de transistores MOSFET en circuitos integrados.Since the invention in 1960 of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the CMOS semiconductor industry has invariably invented new feats to progressively reduce the minimum gate length, from the micrometer scale (< 10-μm) to the nowadays 7-14-nm gate lengths or the new 5-nm technology node predicted to be manufactured in 2020-2021, all with the aim of fabricating more reliable devices and even more advanced circuits and systems, with billions of transistors per chip. With all the benefits that transistor size scaling brings to power, area and performance, approaching the atomic scale poses an important peril: the increase of variations of the transistor’s intrinsic performance, thus critically compromising the fundamental reliability of the fabricated devices and circuits. In this way, variations of fabricated transistor parameters, like for instance threshold voltage or mobility, as well as their degradation during circuit functionality, have become an increasing concern in nanometer integrated circuit design. Moreover, a significant increase of gate leakage current has emerged due to the scaling in the thickness of the transistor’s insulator. In this scenario, to increase performance and reliability of the fabricated devices, new and more complex stack materials have been introduced, such as Silicon oxynitride (SiON), High-K Metal gate insulators (HKMG) and new devices geometries like FinFETs, FDSOI or MuGFETs have emerged in ultra-scaled technology nodes to continue with the scaling trend and have better control of the short channel effects. The variability in the transistor parameters, stochastic by nature, must be massively characterized to capture those variations with a representative and sound statistical sampling. Variability sources are divided in two different types: first, the time-zero variability, typically known as process variability which occurs during the fabrication process and consists in a permanent either random or systematic, shift of the device parameters; second, the time-dependent variability, which occurs during device or circuit operation over time and includes transient effects like Random Telegraph Noise, and degradation mechanisms or aging effects, like Hot Carrier Injection, Bias Temperature Instability, Time Dependent Dielectric Breakdown, Stress Induced Leakage Current, etc., which are potential sources of device and IC variability that can lead transistors to a progressive degradation or to a permanent failure. To reduce or mitigate variability effects, novel variability-aware circuit design techniques are required to assess the combined impact of time-zero and time-dependent variability in advanced technology nodes. Variability-aware techniques utilize accurate compact models, which are based in statistical characterization of individual MOSFET devices. In this regard, providing statistically accurate characterization of TZV and TDV effects in modern CMOS technologies has, therefore, become a key step in the path towards attaining truly reliable integrated circuits. In this context, this thesis will contribute to the characterization and lifetime prediction of nanometer CMOS technologies through a thorough study of an extensive statistical data samples. To do so, issues related to typical serial characterization techniques, which require months or even years of continuous non-stop device testing, are overcome thanks to a novel and versatile array-based IC chip design in conjunction with a full-custom characterization framework. These two key elements, the IC and the framework, can effectively be utilized to statistically characterize the impact of different device variability sources in nanometer-scale MOSFETs while significantly and outstandingly reducing the required characterization time

A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models

.In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.Peer Reviewe

A smart noise- and RTN-removal method for parameter extraction of CMOS aging compact models

.In modern nanometer-scale CMOS technologies, time-zero and time-dependent variability (TDV) effects, the latter coming from aging mechanisms like Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) or Random Telegraph Noise (RTN), have re-emerged as a serious threat affecting the performance of analog and digital integrated circuits. Variability induced by the aging phenomena can lead circuits to a progressive malfunction or failure. In order to understand the effects of the mentioned variability sources, a precise and sound statistical characterization and modeling of these effects should be done. Typically, transistor TDV characterization entails long, and typically prohibitive, testing times, as well as huge amounts of data, which are complex to post-process. In order to face these limitations, this work presents a new method to statistically characterize the emission times and threshold voltage shifts (ΔVth) related to oxide defects in nanometer CMOS transistors during aging tests. At the same time, the aging testing methodology significantly reduces testing times by parallelizing the stress. The method identifies the Vth drops associated to oxide trap emissions during BTI and HCI aging recovery traces while removing RTN and background noise contributions, to avoid artifacts during data analysis.Peer Reviewe

Flexible Setup for the Measurement of CMOS Timedependent Variability with Array-based Integrated Circuits

This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits, through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically timeconsuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signalsPeer reviewe

Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions

In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values.Peer reviewe